Chiisai HAL Driver Modules
This part holds the individual driver specifications — one self-contained chapter per module. Each builds on the shared foundation in General and follows the same structure, so you can navigate any module the same way.
How each module chapter is organized (see How to Read This Specification):
Understand it — the module’s overview & concepts, and the design decisions behind it.
Use it — task-oriented guides for application developers: quickstart, configuration, and per-capability how-tos.
Implement it — the normative reference (API, configuration, errors) and the binding requirements a silicon vendor must satisfy.
The following modules are specified:
Can — a CAN controller abstraction: transmits and receives frames per channel (Classic CAN and CAN FD) and reports bus-off and other events by interrupt or polling.
I2c — an I2C abstraction operating each channel as a controller (master) or a target (slave).
Lin — a LIN responder controller abstraction, covering power-state and transaction handling.
Mcu — the microcontroller’s core facilities: mode/reset management, the clock tree, and the reset cause (single-instance, no channels).
Mem — a memory-technology-agnostic abstraction for reading, writing, erasing, and blank-checking physically segmented memory (typically flash), including suspend/resume.
Port — general-purpose I/O: reads and writes pin and port values, toggles pins, and detects pin edges, with functions and directions established at initialization.
Spi — an SPI abstraction operating each channel as a controller or a target, transferring chunked buffer sets over a chip-select sequence.
Uart — a basic UART abstraction transmitting and receiving byte streams per channel, with independent TX and RX state machines and completion / streaming notifications.
Wdg — a watchdog abstraction that sets the watchdog mode and reset timeout (internal or external watchdog, direct or logical timeout strategy).