Appendix

Glossary

Address Area

A contiguous region of the logical address space, typically combining several physical memory sectors into one logical area.

Bank

A group of sectors that maps to one flash controller, within which read-while-write is not permitted.

Bus Channel

A bus channel serves exactly one physical channel.

Bus controller

A bus controller is the hardware/logic block that manages communication on a bus. It configures timing and modes, controls access to the bus, sends and receives frames, detects errors, and reports status to software via registers or interrupts. It sits between the software stack and the physical layer/transceiver so software can exchange data without dealing with electrical details. A bus controller may consists of one or multiple bus channels of the same type.

CAN L-PDU

A CAN data link layer protocol data unit, consisting of an identifier, a data length, and the data (the SDU).

CAN L-SDU

A CAN data link layer service data unit — the payload transported inside a CAN L-PDU.

Chiisai

Chiisai is a FOSS ecosystem for small microcontrollers. It includes a standard for a HAL and a modular code generation framework used to configure embedded software. The name ‘Chiisai’ is derived from Japanese, meaning ‘small’.

Chiisai Hardware Abstraction Layer

The Chiisai Hardware Abstraction Layer (short: Chiisai HAL) is a standard for small microcontrollers.

Controller/Commander Node

Controller or Commander node (formerly called “master”): Is the bus node that starts and controls a transaction. It provides the clock, selects the Target Node / Responder Node, defines the transfer parameters (timing, mode, length), monitors status and errors, and ends the transaction to release the bus.

Hardware Object

A PDU buffer inside the CAN RAM of a CAN controller or channel.

Hardware Object Handle

A handle representing a transmit or receive hardware object (short: HOH).

interface

A defined contract between software elements that specifies how they interact. It includes the available functions, types, parameters, return values, and required behavior, while hiding the internal implementation.

Page Burst

An aggregation of memory (write) pages accessed together to improve read/write performance.

Port

Several pins grouped together by the hardware and addressed as a unit.

Receive Mailbox

A CAN driver receive mailbox: one or more hardware objects configured as a receive buffer pool, used to optimize software filtering.

Sector

The smallest erasable unit of a memory device (in bytes); may be uniform or variable sized.

Sector Batch

A logical aggregation of uniformly sized sectors.

Sector Burst

An aggregation of sectors accessed together to improve erase performance.

SPI Device

An external device on an SPI bus selected by a chip-select (CS) line. One Controller/Commander Node bus channel may control several SPI devices, one per chip select.

Target/Responder Node

Target or Responder node (formerly called “slave”): Is the addressed device on the bus. It does not start a transaction or provide the clock; instead, it follows the Controller Node’s/Commander Node’s timing, responds to requests, exchanges data as addressed, and completes the requested function. In idle state, it does not drive the bus; when selected, it acknowledges, provides data, or accepts data as defined by the protocol.

Transmit Mailbox

A CAN driver transmit mailbox: one or more hardware objects configured as a transmit buffer pool.

Write Page

The smallest writable unit of a memory device (in bytes).

Abbreviations

<Ci>

Custom Infix

<Ie>

Implementation specific file name Extension

<Ma>

Module Abbreviation

<Mip>

Module Implementation Prefix

<Vi>

Vendor Infix

ABI

Application Binary Interface

ACK

Acknowledgment

API

Application Programming Interface

CAN

Controller Area Network

Chiisai HAL

Chiisai Hardware Abstraction Layer

CS

Chip Select

DLC

Data Length Code

ECC

Error Correction Code

FOSS

Free- and Open-Source Software

GPIO

General Purpose Input/Output

HAL

Hardware Abstraction Layer

HOH

Hardware Object Handle

I2C

Inter-Integrated Circuit

LIN

Local Interconnect Network

MCU

Micro Controller Unit

NACK

Negative Acknowledgment

RX

Reception

SPI

Serial Peripheral Interface

TX

Transmission

UART

Universal Asynchronous Receiver/Transmitter

WDG

Watch DoG