Overview
Informative
What the LIN driver is, its boundaries, and where it sits. Non-binding orientation; the normative contract is in Lin — Requirements. The driver builds on the shared foundation (type system, error model, naming, memory mapping) in General.
In one sentence: the LIN driver (LinDrv) provides a thin, portable abstraction over a LIN
controller operating as a responder — it receives frame headers, transmits or receives the
response, manages per-channel wakeup/sleep, and reports events to the upper layer (LinIf).
What it does
Brings the driver and its channels up and down, and manages per-channel power state (sleep / operational).
Receives a LIN header (break + sync + protected identifier) and, per the upper layer’s decision, transmits, receives, or ignores the response.
Detects and transmits wakeup pulses, and puts a channel into a logical sleep state.
Handles events in either interrupt or polling mode, per channel, and reports them through the
LinIf_On*callbacks.
What it does not do
Responder mode only. The driver does not implement commander (master) behavior: it does not run a schedule table or originate frame headers. See Design Decisions.
No responder node position detection.
No system-resource setup. Input clock, port pins, and interrupt controller are prerequisites another module configures before
Lin_Init.No software PID-parity verification where the hardware cannot provide it.
Where it sits
flowchart TB
UL["Upper layer (LinIf)"]
DRV["Chiisai LIN Driver"]
HWA["Hardware abstraction<br/>(clock, port, interrupt)"]
HW["LIN controller / transceiver"]
UL -->|"Lin_Init, Lin_Wakeup,<br/>Lin_GoToSleepInternal, ..."| DRV
DRV -->|"LinIf_On* callbacks<br/>(OnHeader, OnReception,<br/>OnTransmission, OnError, OnWakeup)"| UL
DRV --> HWA
HWA --> HW
classDef driver fill:#FEDCD2,stroke:#c66,stroke-width:2px;
class DRV driver;
The hardware-abstraction layer (clock, port pins, interrupt controller) is set up by other modules
before Lin_Init; the LIN driver assumes it is ready.
Dependencies
Depends on |
For |
|---|---|
System resources (clock, port, interrupt) |
Bit timing, pin routing, and interrupt configuration for the LIN controller. These must be
set up by another module before |
Expected upper-layer interfaces |
The callbacks and services the driver calls back into ( |
The shared foundation |
The common type system, compiler abstraction, error model, naming scheme, and memory mapping defined in General. |
References
No. |
Document |
|---|---|
[1] |
The Chiisai HAL General part — the shared contract this module builds on. |
[2] |
ISO 17987 (all parts) — Road vehicles — Local Interconnect Network (LIN). |