Overview

Informative

What the SPI driver is, its boundaries, and where it sits. Non-binding orientation; the normative contract is in Spi — Requirements. The driver builds on the shared foundation (type system, error model, naming, memory mapping) in General.

In one sentence: the SPI driver (SpiDrv) provides a thin, portable abstraction over an SPI controller — it transfers data on the SPI bus with each channel acting as a controller or a target, and reports transaction events to the integration code.

What it does

  • Brings the driver and its channels up and down and reports each channel’s state.

  • Transfers data in controller mode (initiates a transaction and drives the chip select) and target mode (responds to a controller that selects it).

  • Carries a transaction as a buffer set — an array of buffer chunks transferred within one chip-select sequence, with independent TX and RX pointers.

  • Handles events in either interrupt or polling mode, per channel, and notifies the integration code via Spi_Callout_OnTransactionEnd (and Spi_Callout_CsControl for GPIO-controlled chip selects).

What it does not do

  • Asynchronous transfers only — every transfer API is non-blocking; there is no synchronous (blocking) transfer service.

  • Full-duplex only — half-duplex operation is out of scope.

  • No chip-select routing logic — where CS is driven by GPIO, the driver only notifies the required CS timing through Spi_Callout_CsControl; the integration code toggles the pin.

  • No higher-level protocol on top of SPI — command sets and register maps belong to the upper layer.

  • No system-resource setup — input clock, port pins, and interrupt controller are prerequisites another module configures before Spi_Init.

Where it sits

        flowchart TB
   INTEG["Integration code<br/>(Spi_Callout_Stubs.c)"]
   IC["Integration code<br/>(CS GPIO control)"]
   DRV["Chiisai SPI Driver"]
   HWA["Hardware abstraction<br/>(clock, port, interrupt)"]
   HW["SPI controller hardware"]

   INTEG -->|"Spi_Init, Spi_StartTransaction,<br/>Spi_CancelTransaction, ..."| DRV
   DRV -->|"Spi_Callout_OnTransactionEnd"| INTEG
   DRV -->|"Spi_Callout_CsControl (GPIO CS)"| IC
   DRV --> HWA
   HWA --> HW

   classDef driver fill:#FEDCD2,stroke:#c66,stroke-width:2px;
   class DRV driver;

The hardware-abstraction layer (clock, port pins, interrupt controller) is set up by other modules before Spi_Init; the SPI driver assumes it is ready.

Dependencies

Depends on

For

System resources (clock, port, interrupt)

Bit timing, pin routing, and interrupt configuration for the SPI controller. These must be set up by another module before Spi_Init.

Callouts and expected interfaces

The services the driver calls back into (Spi_Callout_OnTransactionEnd, Spi_Callout_CsControl, LogM_Report, and optional critical-section services). See API Reference → Callouts the integrator provides.

The shared foundation

The common type system, compiler abstraction, error model, naming scheme, and memory mapping defined in General.

References

No.

Document

[1]

The Chiisai HAL General part — the shared contract this module builds on.