Overview

Informative

What the UART driver is, its boundaries, and where it sits. Non-binding orientation; the normative contract is in Uart — Requirements. The driver builds on the shared foundation (type system, error model, naming, memory mapping) in General.

In one sentence: the UART driver (UartDrv) provides a thin, portable abstraction over a basic UART controller — it transmits and receives byte streams on each channel, driving independent TX and RX flows and reporting completion / streaming events to the integration code.

What it does

  • Brings the driver and its channels up and down (Uart_Init / Uart_DeInit) and reports each channel’s TX and RX state.

  • Transmits a buffer per channel (Uart_StartTxTransaction), notifying either on bus completion (Uart_Callout_OnTransmission) or when the software buffer empties for streaming (Uart_Callout_OnStreamingDataRequest) — one style per channel, chosen by configuration.

  • Receives into a buffer (Uart_StartRxTransaction) with an optional mid-transfer trigger (additionalRxLenTrg) so the integration code can be notified before the buffer fills; supports streaming reception without dropping bytes, plus Uart_CancelRxTransaction.

  • Handles events in either interrupt or polling mode, per channel, and supports optional hardware flow control where the hardware provides it.

What it does not do

  • Basic UART protocol only — no LIN mode, no multi-processor (single-master-multi-slave) mode, no sub-modes such as Smart Card or IrDA.

  • No higher-level protocol — framing, commands, and checksums on top of UART belong to the upper layer.

  • No system-resource setup — input clock, port pins, and interrupt controller are prerequisites another module configures before Uart_Init.

Where it sits

        flowchart TB
   INTEG["Integration code<br/>(Uart_Callout_Stubs.c)"]
   DRV["Chiisai UART Driver"]
   HWA["Hardware abstraction<br/>(clock, port, interrupt)"]
   HW["UART controller hardware"]

   INTEG -->|"Uart_Init, Uart_StartTxTransaction,<br/>Uart_StartRxTransaction, ..."| DRV
   DRV -->|"Uart_Callout_On* callouts<br/>(Reception, Transmission,<br/>StreamingDataRequest)"| INTEG
   DRV --> HWA
   HWA --> HW

   classDef driver fill:#FEDCD2,stroke:#c66,stroke-width:2px;
   class DRV driver;

The hardware-abstraction layer (clock, port pins, interrupt controller) is set up by other modules before Uart_Init; the UART driver assumes it is ready.

Dependencies

Depends on

For

System resources (clock, port, interrupt)

Bit timing, pin routing, and interrupt configuration for the UART controller. These must be set up by another module before Uart_Init.

Callouts and expected interfaces

The callouts and services the driver calls into (Uart_Callout_On*, LogM_Report, and critical-section services). See API Reference → Callouts the integrator provides.

The shared foundation

The common type system, compiler abstraction, error model, naming scheme, and memory mapping defined in General.

References

No.

Document

[1]

The Chiisai HAL General part — the shared contract this module builds on.